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High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics

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Abstract

Vedic Mathematics is the ancient methodology of

Indian mathematics which has a unique technique of calculations

based on 16 Sutras (Formulae). A high speed complex multiplier

design (ASIC) using Vedic Mathematics is presented in this

paper. The idea for designing the multiplier and adderlsubtractor

unit is adopted from ancient Indian mathematics

"Vedas". On account of those formulas, the partial products

and sums are generated in one step which reduces the carry

propagation from LSB to MSB. The implementation of the Vedic

mathematics and their application to the complex multiplier

ensure substantial reduction of propagation delay in comparison

with DA based architecture and parallel adder based

implementation which are most commonly used architectures.

The functionality of these circuits was checked and performance

parameters like propagation delay and dynamic power

consumption were calculated by spice spectre using standard

90nm CMOS technology. The propagation delay of the resulting

(16, 16)x(16, 16) complex multiplier is only 4ns and consume 6.5

mW power. We achieved almost 25% improvement in speed

from earlier reported complex multipliers, e.g. parallel adder and

DA based architectures.

INTRODUCTION

Complex multiplication is of immense importance in

Digital Signal Processing (DSP) and Image Processing (IP).

To implement the hardware module of Discrete Fourier

Transformation (DFT), Discrete Cosine Transformation

(DCT), Discrete Sine Transformation (DST) and modem

broadband communications; large numbers of complex

multipliers are required. Complex number multiplication is

performed using four real number multiplications and two

additions/ subtractions. In real number processing, carry needs

to be propagated from the least significant bit (LSB) to the

most significant bit (MSB) when binary partial products are

added [1]. Therefore, the addition and subtraction after binary

multiplications limit the overall speed. Many alternative

method had so far been proposed for complex number

multiplication [2-7] like algebraic transformation based

implementation[2], bit-serial multiplication using offset binary

and distributed arithmetic [3], the CORDIC (coordinate

rotation digital computer) algorithm [4], the quadratic residue

number system (QRNS) [5], and recently, the redundant

complex number system (RCNS) [6].

MATHEMATICAL FORMULATION OF VEDIC SUTRAS

The gifts of the ancient Indian mathematics in the world

history of mathematical science are not well recognized. The

contributions of saint and mathematician in the field of

number theory, 'Sri Bharati Krsna Thirthaji Maharaja', in the

fonn of Vedic Sutras (fonnulas) [11] are significant for

calculations. He had explored the mathematical potentials

from Vedic primers and showed that the mathematical

operations can be carried out mentally to produce fast answers

using the Sutras. In this paper we are concentrating on

"Urdhva-tiryakbyham", and "Nikhilam Navatascaramam

Dasatah" fonnulas and other fonnulas are beyond the scope of

this paper.

A. "Urdhva-tiryakbyham " Sutra

The meaning of this sutra is "Vertically and crosswise"

and it is applicable to all the multiplication operations. Fig. 1

represents the general multiplication procedure of the 4x4

multiplication. This procedure is simply known as array

multiplication technique [12]. It is an efficient multiplication

technique when the multiplier and multiplicand lengths are

small, but for the larger length multiplication this technique is

not suitable because a large amount of carry propagation

delays are involved in these cases. To overcome this problem

we are describing Nikhilam sutra for calculating the

multiplication of two larger numbers.

Exponent Determinant

The hardware implementation of the exponent

determinant is shown in Fig. 4.The integer part or exponent of

the number from the binary fixed point number can be

obtained by the maximum power of the radix. For the nonzero

input, shifting operation is executed using parallel in

parallel out (PIPO) shift registers. The number of select lines

(in FigA it is denoted as S], So) of the PIPO shifter is chosen

as per the binary representation of the number (N-1)IO. 'Shift'

pin is assigned in PIPO shifter to check whether the number is

to be shifted or not (to initialize the operation 'Shift' pin is

initialized to low). A decrementer [13] has been integrated in

this architecture to follow the maximum power of the radix. A

sequential searching procedure has been implemented here to

search the first 'I' starting from the MSB side by using

shifting technique.

SIMULATION RESULT ANALYSIS

All the algorithm of this paper was simulated and their

functionality was examined by using Spice Spectre.

Performance parameters such as propagation delay and power

consumptions analysis of this paper using standard 90nm

CMOS technology. To evaluate the performance parameters,

we give the values of the computational effort using array

multiplier and Vedic multiplier. As shown, the application of

the Vedic method for mUltiplication cuts the amount of the

hardware as well as increases the performance parameters

such as propagation delay, dynamic switching power

consumptions, and dynamic leakage power consumptions. The

performance parameters analysis using array multiplication

and Vedic multiplication is shown in Table I. Input data is

taken as a regular fashion for experimental purpose. We have

kept our main concentration for reducing the propagation

delay, dynamic switching power and dynamic leakage power

consumption and energy delay product.

CONCLUSION

In this paper we report on a novel complex number

multiplier design based on the formulas of the ancient Indian

Vedic Mathematics, highly suitable for high speed complex

arithmetic circuits which are having wide application in VLSI

signal processing. The implementation was done in Spice spectre

and compared with the mostly used architecture like distributed

arithmetic, parallel adder based implementation, and algebraic

transformation based implementation. This novel architecture

combines the advantages of the Vedic mathematics for

multiplication which encounters the stages and partial product

reduction. The proposed complex number multiplier offered

20% and 19% improvement in terms of propagation delay and

power consumption respectively, in comparison with parallel

adder based implementation. Whereas, the corresponding

improvement in terms of delay and power was found to be

33% and 46% respectively, with reference to the algebraic

transformation based implementation.